1. Field of the Invention
The present invention relates in general to phase detectors and in particular to a phase detector providing output pulses of width proportional to a phase difference between two input signals.
2. Description of Related Art
A phase detector compares two input signals and generates an output signal indicative of their phase difference. Phase detectors are commonly used in phase-locked loop (PLL) circuits as illustrated in FIG. 1. The PLL circuit of FIG. 1 produces an output signal (OUTPUT) having a magnitude proportional to the frequency of an input signal INPUT. A phase detector 10 produces a signal LEAD/LAG indicating whether the INPUT signal leads or lags a signal VCO produced by a voltage-controlled oscillator 12 controlled by the OUTPUT signal. The LEAD/LAG signal tells a charge pump 14 whether to add or remove charge from a capacitor within a low pass filter 16, thereby raising or lowering the voltage of the PLL output signal OUTPUT. The OUTPUT signal controls the frequency of oscillation of the VCO signal. When VCO lags the INPUT signal, phase detector 10 drives LEAD/LAG high telling charge pump 14 to add charge to the capacitor in filter 16. This increases the OUTPUT voltage, thereby increasing the frequency of oscillation of the VCO signal. Conversely, when VCO leads the INPUT signal, phase detector 10 drives LEAD/LAG low telling charge pump 14 to remove charge from the capacitor in filter 16. This decreases the OUTPUT voltage, thereby decreasing the frequency of oscillation of the VCO signal. The OUTPUT signal magnitude stabilizes at a level that frequency locks the VCO signal to the INPUT signal, and is thereby indicative of the frequency of the INPUT signal.
A prior art "type I" phase detector, such as a simple exclusive or (XOR) gate, produces an output LEAD/LAG signal that is always either high or low. Thus charge pump 14 must always be either adding charge to or removing charge from filter 16, even when INPUT and VCO are in phase. Thus the OUTPUT signal tends to jitter. The amount of jitter in the OUTPUT signal can be reduced by increasing the size of the capacitor in filter 16, but a large capacitor can add expense and bulk to the PLL circuit.
U.S. Pat. No. 4,291,274 issued Sep. 22, 1981 to Suzuki et al illustrates a prior art "type II" phase detector. A type II phase detector produces a tri-state output LEAD/LAG signal that tri-states when its two input signals are in phase with one another. The type two phase detector otherwise produces a sequence of pulses in its output LEAD/LAG signal with the sign of the pulses indicating which of its two input signals leads the other and with the width of the pulses indicating the amount of phase difference between the two signals. When phase detector 10 of FIG. 1 is implemented by a type II phase detector, the LEAD/LAG signal spends progressively more of its time in tri-state condition as the frequency of the VCO signal approaches that of the INPUT signal. Thus charge pump 14 spends progressively less of its time pumping charge into or out of filter 16. This greatly reduces jitter in the OUTPUT signal.
While the type II phase detector of the aforementioned patent reduces jitter in the VCO signal, it is substantially more complex than a type I phase detector employing only a single XOR gate. What is needed is a circuit that provides the benefits of a type II phase detector while employing fewer components.